An important phase in integrated circuit (IC) chip design and manufacturing involves implementing a software verification tool to substantiate the functionality of a prototype design prior to fabrication. Chip parameters are specified and are modeled utilizing a high-level hardware description language (HDL), such as Verilog, VHDL, or C functions, to describe the IC at a higher level of abstraction than gates or transistors. Verifying the operations of the prototype prior to fabrication ensures that the requirements defined by the chip specifications are satisfied, from layout to electrical parameters. In particular, the verification process provides feedback to the engineers, so that any detected defects can be corrected. This is potentially critical, since eliminating problems at an early stage results in substantial savings in the time and cost of manufacturing.
Typically, the HDL simulation can be divided into a functional analysis and a timing analysis. The functional analysis verifies that the design logic performs as intended (i.e., whether the chip will work or not) in an “event-driven” asynchronous environment in which information regarding timing is not considered. Each internal component may be assumed to include a given time delay. Alternatively, an output state may incur a timing delay that is different from that of a next output state. Simulated test signals propagate from an input end to an output end of the design to provide output signals that are subsequently compared with predetermined target signals (i.e., anticipated reference signals). Based on any unexpected outputs, design parameters are modified when necessary.
Independent of the functional analysis, the timing analysis focuses on whether the design logic operates within time constraints. This is important, since the prototype must be made compatible with other devices. A timing margin is generated based on factors such as the physical characteristics of the design, including lengths of internal transmission lines and bus specifications. Timing parameters, including propagation delay, strobe time, and setup and hold times are considered.
Data from both the functional analysis and the timing analysis is captured. The captured data may be used by an automatic test generator (ATG) to create test vector files of state data for subsequent physical testing of a device under test (DUT) that is fabricated based on the prototype design. The testing is typically performed by a conventional “time-driven” ATG operating in a synchronous environment in which data is sampled at a predetermined fixed instance in every successive tester cycle.
A concern is that there may be at least one occasion of an inability of the synchronous tester to properly sample DUT data as a result of an asynchronous variability of data from the DUT. Since the tester is configured to sample data at predetermined instances in successive tester cycles while operating in the synchronous environment, the tester is not well adapted for sampling incoming data from the DUT that changes states at unpredictable times due to its asynchronous behavior. This is problematic, because if the timing margin of the DUT does not include a sufficient time period before and after an active tester edge (i.e., Tsetup and Thold) needed by the tester for sampling the output data from the DUT, the tester may exhibit responses that are different from those generated during test simulation. Consequently, the test vectors produced by the ATG based on the simulated data may not trigger the intended behavior within the asynchronous prototype design. Properly identifying the precise placement of the active tester edges for data sampling is often iteration intensive. That is, in attempting to fix the placement of a tester edge to correspond to a sampling instance, the location is often determined by probing one instance after another until an adequate timing is found.
What is needed is a method for test data generation in which timing variability from an asynchronous device can be properly sampled by a synchronous tester.